SP8861

Features

• Improved Digital Phase Detector to Eliminate “Dead Band” Effects
• Low Operating Power, Typically 175mW
• 1.3GHz Operating Frequency
• Complete Phase Locked Loop
• High Input Sensitivity
• Programmed through Three Wire Data Bus
• Wide Range of Reference Division Ratios
• Local Storage for Two Frequency Words giving Rapid Frequency Toggling
• Programmable Phase Detection Gain
• Power Down Mode
• ESD Protection on all Pins

The SP8861 is a low power single chip synthesiser intended for professional radio applications and contains all the elements (apart from the loop amplifier) to fabricate a PLL frequency synthesis loop. The device is serially programmable by a three wire data highway and contains three independent buffers to store one reference divider word and two local oscillator divider words. Two charge pumps, programmable in phase gain are provided to improve lock up performance. The preset tandem operation of the charge pumps can be overwritten, or the comparison frequencies switched to output ports under control of the divider word. The dual modulus ratio and so operating range is also programmable through the same word. A power down mode is incorporated as a battery economy feature.

Prescaler and A-M counter

Reference source and divider

The reference source in the SP8861 is obtained from an on-board oscillator, frequency controlled by an external crystal. The oscillator can also function as a buffer amplifier allowing the use of an external reference source. In this mode, the source is simply AC coupled into the oscillator transistor base on pin 20.
The oscillator output is coupled to a programmable reference divider whose output is the reference for the phase detector. The reference divider is a fully programmable 13-bit asynchronous design and can be set to any division ratio between 1 and 8191. The actual division ratio is controlled by a data word stored in the internal reference buffer.

Phase comparator
The SP8861 is provided with a digital phase comparator feeding two charge pump circuits. Charge pump 1 has preset currents programmable as shown in table 1. Charge pump 2 has a current level set by an external resistor: the current is multiplied by a factor determined by the F1 or F2 word. A look detect circuit is connected to the output of charge pump 2. When the voltage level at pin 25 is between approximately 2.25 and 2.75 volts, pin 27 will be low and charge pump 1 disabled depending on the P01 and P02 programming bits. The output signals from the reference and M counters are available on pins 4 and 5 when programmed by the reference programming word. An external phase detector may be connected to pins 4 and 5 and may be used independently or in conjunction with the on-chip detector. To allow for control direction changes introduced by the design of the control loop, a programming bit in the F1/F2 programming word interchanges the inputs to the on-chip phase detector and reverses the functions on pins 4 and 5.

Data entry and storage
The data section of the SP8861 consists of a data input interface, an internal data shift register and three internal data buffers. Data is entered into the data input interface by a three wire data highway with data, clock and chip enable inputs. The input interface then routes this data to a 24-bit shift register with bus connections to three data buffers. Data entered via the serial bus is transferred to the appropriate data buffer on the negative transition of the chip enable input according to the two final data bits.
The MSB of the data is entered first. The dual F1/F2 buffer can receive two 22 bit words and controls the programmable divider A and M counters using 19-bits, the phase detector gain with two bits and the phase detector sense with one bit. A fourth input from the synthesiser control system selects the active buffer.
The third buffer contains only 16 bits, 13 being used to set the reference counter division ratio, and 2 to control the phase comparator enable logic. The remaining bit sets the dual modulus prescaler N ratio.
The data words may be entered in any individual multiple sequences, and the shift register can be updated while the data buffers retain control of the synthesiser with the previously loaded data. This enables four unique data words to be stored in the device, with three in the data buffers and a fourth in the shift register, while the chip is enabled. The F1 word may also be updated while F2 is controlling the programmable divider and vice versa. The dual F1/F2 buffer enables the device to be toggled between two frequencies using the F1/F2 select input at a rate determined by the comparison frequency and also enables random frequency hopping at a rate determined by a byte load period, since the loop can be locked to F1 whilst F2 is updated by entering new data via the shift register. The F1/F2 input is high to select F1. An F1 or F2 update cycle will consist of a byte containing 24 bits, whereas the reference byte will contain 18 bits. The device requires 3 bytes, each with a chip select sequence, totalling 66 bits to fully program.