SP8685

The SP8685 is an ECL variable modulus divider, with ECL10K compatible outputs. It divides by ten when either of the ECL control inputs PE1 or PE2 is in the high state and by eleven when both are low (or open circuit).

Operating notes

1. The clock input is biased internally and coupled to the signal source with a suitable capacitor. The input signal path is completed by an input reference decoupling capacitor from pin 10 to ground.
2. The device self-oscillate if no signal is present at the input. If this is undesirable, plug in a 15kΩ resistor from the clock input (pin 12) to VEE; this reduces the input sensitivity by approximately 100mV.
3. The circuit operates down to DC, but slew rate must be better than 100V/µs.
4. The outputs are compatible with ECLII but can be interfaced to ECL10K too.
5. The PE inputs are ECLIII/10K compatible and include 4.3kΩ pulldown resistors. Unused inputs can, therefore, be left open.
6. Input impedance is a function of frequency.
7. All components should be suitable for the high-frequency.