- LOW POWER CMOS PROCESS
- PRE-PROGRAMMED ADAPTIVE 3-BIT ALGORITHM
- PERFECT IDLE CHANNEL NOISE PATTERN
- CLOCK FREQUENCIES UP TO 1 MHz
- FLEXIBLE BIASING
- SINGLE INTEGRATION
- SIGNAL ENCODER/DECODER
- COMPLEX WAVEFORM ANALYSIS
- AUDIO DELAY
The input differential amplifier drives a clocked limiter, and this produces the digital output. The sequential signal so produced is analysed by the adaption logic which detects three 'ones’ or ‘zeros' and provides compand outputs. These, when integrated into duplicated RC networks, produce opposite polarity voltages related to the power of the duplicated RC networks, produce opposite polarity voltages related to the power of the input signal. One of these voltages is switched to the “local decoder" RC via the 'pulse height modulator', the polarity of the switched voltage being defined by the logic output. The output from the local decoder is fed to the non-inverting input of the differential amplifier and closely tracks the input signal. The maximum and minimum difference voltage between the compand capacitors defines the dynamic range of the pulse height, and saturated switching ensures this is maximised, the complementary process ensures a highly symmetrical output pulse.
When operating as a decoder similar circuitry is used with the feedback loop open circuit and the digital signal fed in via the input amplifier, the logic threshold being defined by the other input of the amplifier.